1. Field of the Invention
The present invention relates to VLSI chips in general and more particularly to CMOS driver circuits used in said chips.
2. Background of the Invention
CMOS circuits or components have become the preferred building blocks for fabricating VLSI chips. CMOS VLSI chips are preferred because the circuits are low powered and relatively fast. Among the various CMOS building blocks is the output circuit which is referred to as an off-chip driver (OCD). The OCDs are used for driving circuits on other chips or high capacitances loaded internal net on the same VLSI chip.
A conventional CMOS OCD circuit has a pair of series connected P-channel and N-channel devices. Each device has a gate (G) electrode, a source (S) electrode and a drain (D) electrode. The devices are connected so that the gate electrodes are connected to an input node. the source electrode of the P-channel device is connected to a positive rail of a power supply. The source electrode of the N-channel device is connected to a negative rail of the power supply. The drain electrodes of the devices are connected to an output node. If an input voltage is applied to the input node, when the voltage is at ground potential, the P-channel device is turned on, the N-channel device is turned off and the output node is at the positive power supply voltage level.
Likewise, when the input voltage reaches the positive power supply voltage level, the P-channel device is turned off. The N-channel device is turned on and the output node swings to the negative power supply voltage level. As the input voltage swings between ground and a positive value (say Vcc), the P-channel and N-channel devices conduct simultaneously to cause a large current spike (di/dt). The large di/dt current causes noise in the system.
The rapid switching of the output devices between ground potential and Vcc is another source of noise in CMOS driver circuits. As the output changes states, the device draws a relatively large amount of current. The changing current (di/dt) excites the inductance between the chip and the board causing the chip's ground to rise, or "bounce". Inductance of the package pins can cause transient variations in the ground and voltage potentials seen by the chip circuits as higher current off chip driver circuits switch on and off. These drivers cause large di/dt values as they charge and discharge the capacitance seen at the output pins.
The electrical noise that is caused by the above described phenomenon causes a variety of problems. One of the obvious problems is radiation which has to be minimized to meet FCC EMI standards. Other problems include false detection of signal transitions due to ground bounce, input signal level-shift, etc. A more detailed description of ground bounce and related problems are set forth in an article entitled "EDN's Advance CMOS Logic GroundBound Tests," by David Shear, EDN Mar. 2, 1989, (p. 88).
The prior art sets forth several techniques for controlling the large di/dt current caused by simultaneous conduction of series connected FETs. Even though the prior art circuits differ in details, the general approach is to provide circuit arrangements that control the simultaneous conduction of the series connected FETs. Examples of the prior art techniques are set forth in U.S. Pat. Nos. 4,818,901, 4,806,802, 4,806,794, 4,800,298, 4,761,572, 4,758,743, 4,638,187, 4,274,014, 3,651,340, 3,631,528 and JP60-141020. Even though the prior art circuits work well for its intended purpose, the circuits tend to be complicated and difficult to implement with CMOS technology. Even if the circuits' implementations are relatively easy, they usually require unnecessary amount of surface area which is usually a scarce commodity in LSI chip design.
Another source of electrical noise in LSI circuit design is caused by interconnecting module leads of circuit boards. These strip lines exhibit behavior analogous to transmission lines. U.S. Pat. No. 4,749,882 discloses a device implemented in CMOS technology, for controlling this type of noise. The device consists of an input inverter circuit stage that controls the slope of an output signal from the inverter stage produced in response to an input signal.
U.S. Pat. No. 4,567,378 describes a driver circuit with a feedback loop that controls the output device so that the rise and fall times of the output signal matches that of an input signal.
IBM Technical Disclosure Bulletin, Vol. 27, No. 12, May, 1985 at page 7247 by C. K. Erdelyi, describes a driver circuit topology wherein cascaded pairs of devices sequence an input signal to an output node. An independent resistor (R) is connected to the control gate of each device.
An article by E. H. Stoops, IBM Technical Disclosure Bulletin, Vol. 27, No. 1A, June, 1984 (page 13), describes a circuit that controls the time rate of change of current in the active device in the output stage of an FET off-chip driver.
An article entitled "Raised Cosine Driver/Transmitter," in Research Disclosure, March, 1988, No. 287 describes a circuit in which a signal waveform is generated by switching independent current sources between two reference voltage levels.